Without getting too deep into semiconductor theory and other EE stuff, switching losses are a function of FET capacitance in addition to FET resistance.

Paralleling FETs opens another can of worms but ultimately you have to ensure that the FET(s) observe what is known as SOA (safe operating area)
You also have to manage power dissipation and thermal design

Clearly Jeti missed something in their analysis and it’s a bit disappointing to be honest. Without seeing a schematic I can’t tell exactly.

Disclaimer: I’m one of those EE types and I’ve designed brushless motor controllers in my past.