The only one that I am involved with is the JR PLL Module. The principle of operation is fairly simple, on the rear of the module are 2 decade switches. These are read on switch on by a microprocessor and outputs clock and data to a variable phase comparator. The data stream tells the comparator what division ratio to set itself to. Another input to this comparator is a 13 MHz crystal, this is divided down internally and becomes the reference signal.
The last input to this IC is a sample from the RF Oscillator. This oscillator is controlled by a varactor diode which is biased by the output of the comparator. As the oscillator starts up, the sample is divided down ( ratio as set by the data stream from the microprocessor ) and is compared against the reference frequency. If the phase is different then the output from the comparator will adjust the biasing on the varactor diode which in turn adjusts the oscillator frequency.
Meanwhile, the DC power to the RF Amplifier is switched off via a simple CR timer. The timer allows sufficient time for the RF Oscillator to settle before powering up the RF Amps.
Should an incorrect channel be assigned via the 2 switches, the microprocessor detects this and prevents the RF Oscillator and Amplifiers from powering up.
The Data stream from the micro is only sent on power up, therefore if the switches are moved during transmission, nothing will happen and the module continues to transmit on its initial channel.
The actual RF frequency generated by the oscillator is ( in the case of the 72MHz variant ) at about 18 MHz. The RF Amps will double this freq, filter, double again, filter then amplify prior to being fed to the Antenna stage.
I may be slightly incorrect on that last part, I am not 100% certain on how many times it is doubled.
