Originally Posted by
dbsonic
I suspect hold times and other functional DRC on sequential logic checked only up to 5.5 volt best case(FF) corner is what that says. Basically, depending which part of the wafer process distribution the die comes from it may operate "flaky" over 5.5v.
Yep that's my guess too. Even if the public documentation had some 10% safety margin it would mean 6.05V. And this eGear system is running with 6.2-6.3 by design.
As a result noone can trust on the sw execution at all, potential problems may be hidden long time due to watchdog etc but when **** hits the fan wrong FETs gets invalid control signal and we have a fire. I didn't even try to explain process verification facts for the persons in question as they really had a thinking that it works perfectly in their own tests so there can't be a problem. LOL.