The trigger circuit will go into a latch chip as Terry has already said. But this circuit will become unlatched after a time delay governed by a R-C network. "Latches" are chips that can be bought at Radio shack. R-C networks are a combination of a resistor and a capacitor value that will give the proper "delay-off". When the resistor and capacitor are in "series", the capacitor will not conduct until it charges up. The resistor will vary the time required to charge the capactor. We should be able to find a acceptable time value versus the rpm of the engine? In other words, the "Latch-On" chip will be energized, but when the "R-C" circuit energizes, it will "Unlatch" the Tigger circuit. The chip packages usually have typical circuit diagrams on them. Radio Shack, at one time, had a logic circuit book with typical diagrams.

74HCT259 8-Bit Addressable Latch
16 Pin DIP $1.29 Catalog #: 276-2868
The RCA CD54/74HC259 and CD54/74HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.
This latch has three active modes and one reset mode. When both Latch Enable (LE\) and Master Reset (MR\) inputs are low, (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR\ and LE\ are high (Memory mode), all outputs are isolated from the Data input; ie, all latches hold the last data presented before the LE\ transition from low to high. A condition of LE\ low and MR\ high (Addressable Latch mode) allows the addressed latch's output to follow the data input;all other latches are unaffected. The Reset mode (all outputs low) results with LE\ is high and MR\ is low.


Jim